PhiPhase Limited


About PhiPhase

PhiPhase Limited was formed in 2016 by Adrian Nash to provide independent consultancy services to the space industry in the fields of spacecraft communications, space electronics design and systems engineering. Adrian has over 30 years of experience in Wireless systems design and Digital Signal Processing (DSP), software and hardware including significant experience in the space industry.

Phiphase Limited has gained a lot of experience working on customer proposals and internal technology for our Clients. This includes CCSDS/ECSS TT&C, telemetry downlinks, AIS payloads, VDES payloads, IoT, RF development, build and simulation (including EM), FPGA design and simulation (in HLS and VHDL) and software design. Below are summaries of a few flagship projects that we have been involved with.

Projects at COM DEV

Adrian originally worked for COM DEV in Stoke Mandeville UK as its Data links product stream Chief Engineer. At COM DEV, Adrian has been the systems architect and lead engineer on the following programmes whilst at COM DEV:

Flexible, Autonomous X-band TT&C (with Zelinda)

Phiphase Limited have been involved with the design of an ESA TRP-funded research project:Flexible, Autotomous TT&C, (“FAT”) in collaboration with Zelinda (Ireland) Ltd and Honeywell Aerospace, taking the concept to TRL4 by building a breadboard. The FAT employs advanced DSP techniques to enable it to autonomously detect the modulation scheme and data rate of uplink transmissions in deep space research (DSSR), Earth Exploration (EES) and Near Earth Space Research (NESR) configurations. Adrian led the project whilst still working at Honeywell, developing the user requirements, equipment requirements and the overall architecture for an X-band configuration of the FAT. Later in collaboration with Zelinda, Adrian developed the FPGA designs for the autonomous carrier acquisition and Direct Sequence Spread Spectrum acquisition modules in MATLAB/VHDL and the application control software written in Java.

AIS Payloads

Phiphase Limited  helped produce a 3U AIS spacecraft design  to an Orbcomm specification. Orbcomm specified a 3-element crossed Yagi as the antenna system so the deployed antenna will be larger than the spacecraft – a flying antenna!

Phiphase Limited produced the initial technical proposal/technical RFP for the payload, then developed the dual-chain RF Front end, 3-AIS receiver (2 COTS + 1 SDR) payload including FPGA firmware and Linux-based software.

Phiphase not only designed the LNA and the SDR’s DSP and user interface but also characterised the breadboard, EM, COTS AIS receivers and SDR over temperature. We worked closely with our Client and their Customer from start to finish.

See our Client’s press release.

IoT Payloads

The 6U UHF ISM-band IoT spacecraft will provide “space-as-a-service” to our Client’s customer. Phiphase Limited produced the initial proposal/RFP for the IoT payload, then after our Client was accepted to produce the spacecraft, we designed and characterised the RF Front End (RFFE) and wrote the internal requirement specifications for our Client and their antenna subcontractor.

The UHF RFFE combines a complex, deployable antenna system comprising two receive antennas and a transmitting antenna and RFFE payload electronics  (dual-chain LNA, calibration system and GaN-based SSPA). The RFFE is designed to interface directly with a Software Defined Radio (SDR) that uses a cutting-edge FinFET Xilinx MPSoC with TID and SEE mitigation.

See our Client’s press release.

X-band Downlink Transmitter Proposal

Phiphase Limited in conjunction with Zelinda (Ireland) produced a technical proposal for an 500Mbps X-band transmitter for small satellites that is CCSDS compatible.

The technical proposal was based on a Xilinx FPGA and an RF D/A converter. The much- simplified architecture exploited the FPGA and D/A converter to produce on-channel modulation between 8025 and 8400 MHz. PhiPhases’s contribution was a user-programmable digital 4D-TCM or OQPSK modulator and square-root raised cosine (SRRC) polyphase filter. The filter offered a choice of roll-off factors and its symbol rate was fully programmable up to 500Mbps. The working (placed and routed) FPGA design was developed using Xilinx’s High-Level Synthesis (HLS) design-flow and verified with MATLAB (R) and a Verilog model of the D/A converter’s JESD204b interface.

The proposal was produced for Honeywell Aerospace.

Our Client List

Phiphase Limited specialise in consultancy and design services, including helping our Clients to win new business. Our Client list includes: